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The instruction set of 80386 contains all the instructions supported by·80286. The 80286 instructions are designed to operate with 8-bit or 16-bit data, while the same mnemonics for 80386 instruction set may be executed over 32-bit operands, besides 8-bit and 16-bit operands.
The newly added instructions may be categorized into the following functional groups.
1. Bit scan instructions
2. Bit test instructions
3. Conditional set byte instructions
4. Shift double instructions
5. Control transfer via gates instructions.
1. Bit Scan Instructions: 80386 instruction set has two bit scan mnemonics, such as BSF (bit scan forward) and BSR (bit scan reverse). Both of these instructions scan the operand for a '1' bit, without actually rotating it. The BSF instruction scans the operand from right to left. If a '1' is encountered during the scan, zero flag is set and the bit position of '1' is stored into the destination operand. If no '1' is encountered, zero flag is reset. The BSR instruction also performs the same function but scans the source operand from the left most bit towards right.
2. Bit Test Instructions: 80386 have four bit test instructions, those are BT (test a bit), BTC (test a bit and complement), BTR (test and reset a bit) and BTS (test and set a bit). All these instructions test a bit position in the destination operand, specified by the source operand. If the bit position of the destination operand specified by the source operand satisfies the condition specified in the mnemonic, the carry flag is affected appropriately. For example, in the case of BT instruction, if the bit position in the destination operand, specified by the source operand, is '1', the carry flag is set, otherwise, it is cleared.
3. Conditional Set Byte instruction: This instruction sets all the operand bits, if the condition specified by the mnemonic is true. This instruction group has 16 mnemonics corresponding to 16 conditions as shown below.
E.g. SETO EAX; this instruction sets all the bits of EAX, if the overflow flag is set.
1. SETO Set on overflow
2. SETNO Set on no overflow
3. SETB/SETNAE Set on below/not above or equal
4. SETNB/SETAE Set on not below/above or equal
5. SETE/SETZ Set on equal/zero
6. SETNE/SETNZ Set on not equal/not zero
7. SETBE/SETNA Set on below or equal/not above
8. SETNBE/SETA Set on not below or equal/above
9. SETS Set on sign
10. SETNS Set on not sign
11. SETP/SETPE Set on parity/parity even
12. SETNP Set on not parity/parity odd
13. SETUSETNGE Set on less/not greater or equal
14. SETNUSET GE Set on not less/greater or equal
15. SETLE/SETNG Set on less or equal/not greater
16. SETNLE/SETG Set on not less or equal/greater
4. Shift Double Instructions: These instructions shift the specified number of bits from the source operand into the destination operand. The 80386 instruction set has two mnemonics under this category, such as SHLD (shift left double) and SHRD (shift right double). The SHLD instruction shifts the specified number of bits (in the instruction) from the upper side, i.e. MSB of the source operand into the lower side, i.e. LSB of the destination operand. The SHRD instruction shifts the number of bits specified in the instruction from the lower side, i.e. LSB of the source operand into the upper side, .i.e. MSB of the destination operand.
Ex: 1. SHLQ EAX, ECX, 5; This instruction shifts 5 MSB bits of ECX into the LSB positions of EAX one by one starting from the MSB of ECX. 2. SHRD EAX, ECX, 8; this instruction shifts 8 LSB bits of ECX into the MSB positions of EAX one by one starting from the LSB of ECX.
5. Control Transfer Instructions: The 80386 instruction set does not have any additional instructions for the intrasegment jump. However, for intersegment jumps, it has got a set of new instructions which are variations of the previous CALL and JUMP instructions, and are to be executed only in the protected mode. These instructions are used by 80386 to transfer the control either at the same privilege or at a different privilege level. Also, different versions of control transfer instructions are available to switch between the different task types and TSS (task state segment). The corresponding RET instructions are also available to switch back from the new task initiated via CALL, JMP or INT instructions to the parent task. Intel's 80387 has eight 80-bit floating point data registers, which are used to store signed 80-bit data in the form of exponent and significant. Each of these registers has a corresponding 2-bit tag field. The 80387 has a 16-bit control, status and tag word registers. The 80387 has two more 48-bit registers called as instruction and data pointers. The instruction and data pointer registers respectively point to the failing math coprocessor instruction and the corresponding numeric data, which is referred by the CPU. Two bits are allotted for each of the registers R0-R7 in the tag word. Also the tag bits can be used by the exception handlers to check the contents of a stack location without any manipulation. The status word represents the overall status of the coprocessor.
The 80387 can be configured by loading a control word from memory to its control word register. The control word register has exactly similar format as that of 80287.
The newly added instructions may be categorized into the following functional groups.
1. Bit scan instructions
2. Bit test instructions
3. Conditional set byte instructions
4. Shift double instructions
5. Control transfer via gates instructions.
1. Bit Scan Instructions: 80386 instruction set has two bit scan mnemonics, such as BSF (bit scan forward) and BSR (bit scan reverse). Both of these instructions scan the operand for a '1' bit, without actually rotating it. The BSF instruction scans the operand from right to left. If a '1' is encountered during the scan, zero flag is set and the bit position of '1' is stored into the destination operand. If no '1' is encountered, zero flag is reset. The BSR instruction also performs the same function but scans the source operand from the left most bit towards right.
2. Bit Test Instructions: 80386 have four bit test instructions, those are BT (test a bit), BTC (test a bit and complement), BTR (test and reset a bit) and BTS (test and set a bit). All these instructions test a bit position in the destination operand, specified by the source operand. If the bit position of the destination operand specified by the source operand satisfies the condition specified in the mnemonic, the carry flag is affected appropriately. For example, in the case of BT instruction, if the bit position in the destination operand, specified by the source operand, is '1', the carry flag is set, otherwise, it is cleared.
3. Conditional Set Byte instruction: This instruction sets all the operand bits, if the condition specified by the mnemonic is true. This instruction group has 16 mnemonics corresponding to 16 conditions as shown below.
E.g. SETO EAX; this instruction sets all the bits of EAX, if the overflow flag is set.
1. SETO Set on overflow
2. SETNO Set on no overflow
3. SETB/SETNAE Set on below/not above or equal
4. SETNB/SETAE Set on not below/above or equal
5. SETE/SETZ Set on equal/zero
6. SETNE/SETNZ Set on not equal/not zero
7. SETBE/SETNA Set on below or equal/not above
8. SETNBE/SETA Set on not below or equal/above
9. SETS Set on sign
10. SETNS Set on not sign
11. SETP/SETPE Set on parity/parity even
12. SETNP Set on not parity/parity odd
13. SETUSETNGE Set on less/not greater or equal
14. SETNUSET GE Set on not less/greater or equal
15. SETLE/SETNG Set on less or equal/not greater
16. SETNLE/SETG Set on not less or equal/greater
4. Shift Double Instructions: These instructions shift the specified number of bits from the source operand into the destination operand. The 80386 instruction set has two mnemonics under this category, such as SHLD (shift left double) and SHRD (shift right double). The SHLD instruction shifts the specified number of bits (in the instruction) from the upper side, i.e. MSB of the source operand into the lower side, i.e. LSB of the destination operand. The SHRD instruction shifts the number of bits specified in the instruction from the lower side, i.e. LSB of the source operand into the upper side, .i.e. MSB of the destination operand.
Ex: 1. SHLQ EAX, ECX, 5; This instruction shifts 5 MSB bits of ECX into the LSB positions of EAX one by one starting from the MSB of ECX. 2. SHRD EAX, ECX, 8; this instruction shifts 8 LSB bits of ECX into the MSB positions of EAX one by one starting from the LSB of ECX.
5. Control Transfer Instructions: The 80386 instruction set does not have any additional instructions for the intrasegment jump. However, for intersegment jumps, it has got a set of new instructions which are variations of the previous CALL and JUMP instructions, and are to be executed only in the protected mode. These instructions are used by 80386 to transfer the control either at the same privilege or at a different privilege level. Also, different versions of control transfer instructions are available to switch between the different task types and TSS (task state segment). The corresponding RET instructions are also available to switch back from the new task initiated via CALL, JMP or INT instructions to the parent task. Intel's 80387 has eight 80-bit floating point data registers, which are used to store signed 80-bit data in the form of exponent and significant. Each of these registers has a corresponding 2-bit tag field. The 80387 has a 16-bit control, status and tag word registers. The 80387 has two more 48-bit registers called as instruction and data pointers. The instruction and data pointer registers respectively point to the failing math coprocessor instruction and the corresponding numeric data, which is referred by the CPU. Two bits are allotted for each of the registers R0-R7 in the tag word. Also the tag bits can be used by the exception handlers to check the contents of a stack location without any manipulation. The status word represents the overall status of the coprocessor.
The 80387 can be configured by loading a control word from memory to its control word register. The control word register has exactly similar format as that of 80287.
You cannot believe in God until you believe in yourself.@VIVEKANADA
The instruction set of 80386 contains all the instructions supported by·80286. The 80286 instructions are designed to operate with 8-bit or 16-bit data, while the same mnemonics for 80386 instruction set may be executed over 32-bit operands, besides 8-bit and 16-bit operands.
The newly added instructions may be categorized into the following functional groups.
1. Bit scan instructions
2. Bit test instructions
3. Conditional set byte instructions
4. Shift double instructions
5. Control transfer via gates instructions.
1. Bit Scan Instructions: 80386 instruction set has two bit scan mnemonics, such as BSF (bit scan forward) and BSR (bit scan reverse). Both of these instructions scan the operand for a '1' bit, without actually rotating it. The BSF instruction scans the operand from right to left. If a '1' is encountered during the scan, zero flag is set and the bit position of '1' is stored into the destination operand. If no '1' is encountered, zero flag is reset. The BSR instruction also performs the same function but scans the source operand from the left most bit towards right.
2. Bit Test Instructions: 80386 have four bit test instructions, those are BT (test a bit), BTC (test a bit and complement), BTR (test and reset a bit) and BTS (test and set a bit). All these instructions test a bit position in the destination operand, specified by the source operand. If the bit position of the destination operand specified by the source operand satisfies the condition specified in the mnemonic, the carry flag is affected appropriately. For example, in the case of BT instruction, if the bit position in the destination operand, specified by the source operand, is '1', the carry flag is set, otherwise, it is cleared.
3. Conditional Set Byte instruction: This instruction sets all the operand bits, if the condition specified by the mnemonic is true. This instruction group has 16 mnemonics corresponding to 16 conditions as shown below.
E.g. SETO EAX; this instruction sets all the bits of EAX, if the overflow flag is set.
1. SETO Set on overflow
2. SETNO Set on no overflow
3. SETB/SETNAE Set on below/not above or equal
4. SETNB/SETAE Set on not below/above or equal
5. SETE/SETZ Set on equal/zero
6. SETNE/SETNZ Set on not equal/not zero
7. SETBE/SETNA Set on below or equal/not above
8. SETNBE/SETA Set on not below or equal/above
9. SETS Set on sign
10. SETNS Set on not sign
11. SETP/SETPE Set on parity/parity even
12. SETNP Set on not parity/parity odd
13. SETUSETNGE Set on less/not greater or equal
14. SETNUSET GE Set on not less/greater or equal
15. SETLE/SETNG Set on less or equal/not greater
16. SETNLE/SETG Set on not less or equal/greater
4. Shift Double Instructions: These instructions shift the specified number of bits from the source operand into the destination operand. The 80386 instruction set has two mnemonics under this category, such as SHLD (shift left double) and SHRD (shift right double). The SHLD instruction shifts the specified number of bits (in the instruction) from the upper side, i.e. MSB of the source operand into the lower side, i.e. LSB of the destination operand. The SHRD instruction shifts the number of bits specified in the instruction from the lower side, i.e. LSB of the source operand into the upper side, .i.e. MSB of the destination operand.
Ex: 1. SHLQ EAX, ECX, 5; This instruction shifts 5 MSB bits of ECX into the LSB positions of EAX one by one starting from the MSB of ECX. 2. SHRD EAX, ECX, 8; this instruction shifts 8 LSB bits of ECX into the MSB positions of EAX one by one starting from the LSB of ECX.
5. Control Transfer Instructions: The 80386 instruction set does not have any additional instructions for the intrasegment jump. However, for intersegment jumps, it has got a set of new instructions which are variations of the previous CALL and JUMP instructions, and are to be executed only in the protected mode. These instructions are used by 80386 to transfer the control either at the same privilege or at a different privilege level. Also, different versions of control transfer instructions are available to switch between the different task types and TSS (task state segment). The corresponding RET instructions are also available to switch back from the new task initiated via CALL, JMP or INT instructions to the parent task. Intel's 80387 has eight 80-bit floating point data registers, which are used to store signed 80-bit data in the form of exponent and significant. Each of these registers has a corresponding 2-bit tag field. The 80387 has a 16-bit control, status and tag word registers. The 80387 has two more 48-bit registers called as instruction and data pointers. The instruction and data pointer registers respectively point to the failing math coprocessor instruction and the corresponding numeric data, which is referred by the CPU. Two bits are allotted for each of the registers R0-R7 in the tag word. Also the tag bits can be used by the exception handlers to check the contents of a stack location without any manipulation. The status word represents the overall status of the coprocessor.
The 80387 can be configured by loading a control word from memory to its control word register. The control word register has exactly similar format as that of 80287.
The newly added instructions may be categorized into the following functional groups.
1. Bit scan instructions
2. Bit test instructions
3. Conditional set byte instructions
4. Shift double instructions
5. Control transfer via gates instructions.
1. Bit Scan Instructions: 80386 instruction set has two bit scan mnemonics, such as BSF (bit scan forward) and BSR (bit scan reverse). Both of these instructions scan the operand for a '1' bit, without actually rotating it. The BSF instruction scans the operand from right to left. If a '1' is encountered during the scan, zero flag is set and the bit position of '1' is stored into the destination operand. If no '1' is encountered, zero flag is reset. The BSR instruction also performs the same function but scans the source operand from the left most bit towards right.
2. Bit Test Instructions: 80386 have four bit test instructions, those are BT (test a bit), BTC (test a bit and complement), BTR (test and reset a bit) and BTS (test and set a bit). All these instructions test a bit position in the destination operand, specified by the source operand. If the bit position of the destination operand specified by the source operand satisfies the condition specified in the mnemonic, the carry flag is affected appropriately. For example, in the case of BT instruction, if the bit position in the destination operand, specified by the source operand, is '1', the carry flag is set, otherwise, it is cleared.
3. Conditional Set Byte instruction: This instruction sets all the operand bits, if the condition specified by the mnemonic is true. This instruction group has 16 mnemonics corresponding to 16 conditions as shown below.
E.g. SETO EAX; this instruction sets all the bits of EAX, if the overflow flag is set.
1. SETO Set on overflow
2. SETNO Set on no overflow
3. SETB/SETNAE Set on below/not above or equal
4. SETNB/SETAE Set on not below/above or equal
5. SETE/SETZ Set on equal/zero
6. SETNE/SETNZ Set on not equal/not zero
7. SETBE/SETNA Set on below or equal/not above
8. SETNBE/SETA Set on not below or equal/above
9. SETS Set on sign
10. SETNS Set on not sign
11. SETP/SETPE Set on parity/parity even
12. SETNP Set on not parity/parity odd
13. SETUSETNGE Set on less/not greater or equal
14. SETNUSET GE Set on not less/greater or equal
15. SETLE/SETNG Set on less or equal/not greater
16. SETNLE/SETG Set on not less or equal/greater
4. Shift Double Instructions: These instructions shift the specified number of bits from the source operand into the destination operand. The 80386 instruction set has two mnemonics under this category, such as SHLD (shift left double) and SHRD (shift right double). The SHLD instruction shifts the specified number of bits (in the instruction) from the upper side, i.e. MSB of the source operand into the lower side, i.e. LSB of the destination operand. The SHRD instruction shifts the number of bits specified in the instruction from the lower side, i.e. LSB of the source operand into the upper side, .i.e. MSB of the destination operand.
Ex: 1. SHLQ EAX, ECX, 5; This instruction shifts 5 MSB bits of ECX into the LSB positions of EAX one by one starting from the MSB of ECX. 2. SHRD EAX, ECX, 8; this instruction shifts 8 LSB bits of ECX into the MSB positions of EAX one by one starting from the LSB of ECX.
5. Control Transfer Instructions: The 80386 instruction set does not have any additional instructions for the intrasegment jump. However, for intersegment jumps, it has got a set of new instructions which are variations of the previous CALL and JUMP instructions, and are to be executed only in the protected mode. These instructions are used by 80386 to transfer the control either at the same privilege or at a different privilege level. Also, different versions of control transfer instructions are available to switch between the different task types and TSS (task state segment). The corresponding RET instructions are also available to switch back from the new task initiated via CALL, JMP or INT instructions to the parent task. Intel's 80387 has eight 80-bit floating point data registers, which are used to store signed 80-bit data in the form of exponent and significant. Each of these registers has a corresponding 2-bit tag field. The 80387 has a 16-bit control, status and tag word registers. The 80387 has two more 48-bit registers called as instruction and data pointers. The instruction and data pointer registers respectively point to the failing math coprocessor instruction and the corresponding numeric data, which is referred by the CPU. Two bits are allotted for each of the registers R0-R7 in the tag word. Also the tag bits can be used by the exception handlers to check the contents of a stack location without any manipulation. The status word represents the overall status of the coprocessor.
The 80387 can be configured by loading a control word from memory to its control word register. The control word register has exactly similar format as that of 80287.
You cannot believe in God until you believe in yourself.@VIVEKANADA
Microprocessor History
80386 Instruction Set Ppt Chapter 17 80386 Instruction Set. Fairy tail dragon cry english. This chapter presents instructions for the 80386 in alphabetical order. For each instruction, the forms are given for each operand combination, including object code produced, operands required, execution time, and a description. 11.3.5 80386 Instruction Set. The 80386 can execute all 16-bit instructions in real and protected modes. This is provided in order to make the 80386 software compatible with the 8086. The 80386 uses either 8- or 32-bit displacements and any register as the base or index register while executing 32-bit code.
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